Download e-book for iPad: Advanced Computer Architecture: 10th Annual Conference, ACA by Junjie Wu, Haibo Chen, Xingwei Wang

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By Junjie Wu, Haibo Chen, Xingwei Wang

ISBN-10: 3662444909

ISBN-13: 9783662444900

ISBN-10: 3662444917

ISBN-13: 9783662444917

This e-book constitutes the refereed complaints of the tenth Annual convention on complicated desktop structure, ACA 2014, held in Shenyang, China, in August 2014. the nineteen revised complete papers awarded have been rigorously reviewed and chosen from one hundred fifteen submissions. The papers are prepared in topical sections on processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and knowledge facilities; strength and reliability; intelligence computing and cellular computing.

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Additional info for Advanced Computer Architecture: 10th Annual Conference, ACA 2014, Shenyang, China, August 23-24, 2014. Proceedings

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Operation condition is worst. We can see the area and latency increase because of the CFU qualitatively. 2 25 Effect of the CFU For this experiment, we consider the effect of the CFU. The experimental architectures are DSP-ACRP and SHA-ACRP described in previous section. The reference reconfigurable architecture for DSP-ACRP named DSP-RP is a reconfigurable pipeline without CFUs, which contains 8 SPEs. The hardware resources of DSP-RP are roughly equal to the DSP-ACRP which contains 6 SPEs and 2 CFUs.

But it is possible that two iterations are mapped onto the DSP-ACRP at one time because of the hardware resources increase. So performance of DSP-ACRP in this case is double that of DSP-RP. It is much the same when mapping the Over kernel to DSP-ACRP which also contains 5 operations. SHA-RP SHA-ACRP 30 20 10 0 MD5 SHA1 SHA256 SHA512 Fig. 5. Performance comparison with and without CFUs for SHA In the preceding experiments, hardware resources determine the II which is greatly important for performance.

Data exchanged between cores are shared by some processor cores. In most cases, however, cores cannot simultaneously access the data, but do the data by turns. With this feature, the paper presents the SRS model. Shared memory system built on the SRS model can avoid cache coherence between many processor cores altogether, thereby reducing implementation costs. After having been extended, the SRS model can also be applied to process read-only data, private data, global data used for synchronization.

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Advanced Computer Architecture: 10th Annual Conference, ACA 2014, Shenyang, China, August 23-24, 2014. Proceedings by Junjie Wu, Haibo Chen, Xingwei Wang


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